1. Technical Field
The present invention relates to a method and system for power management, and in particular to an improved method and system for dynamic power management of a banked cache memory. Still more particularly, the present invention relates to a method and system for dynamically selecting a maximum number of accessible banks of memory per cycle within a banked cache memory such that the number of bank accesses per cycle are maximized while maintaining an acceptable power application to each of the banks of memory of the banked cache memory.
2. Description of the Related Art
As is well known in the art, random access memories (RAM) are typically semi-conductor based memory that can be read from and written to by the central processing unit and other hardware devices. The storage locations within RAM can be accessed in any order. For example, one type of RAM which is well known in the art is a dynamic RAM (DRAM). Dynamic RAM is typically utilized for storing large increments of data.
Typically, multiple banks of DRAM are manufactured together on a board or chip. In particular, DRAMs store information in integrated circuits containing capacitors. Because capacitors lose their charge over time, DRAM chips typically include logic to refresh each DRAM bank. While a DRAM bank is being refreshed, the bank cannot be read by the processor which leads to wait states while the DRAM banks are being refreshed. Typically, a controller associated with the banked DRAM controls the flow of data to and from each bank within the banked DRAM and determines when power refreshing of each bank occurs. If more banks are being accessed for read, write or refresh during a single cycle than power is provided to refresh in a subsequent cycle, power rail collapse occurs, which degrades the performance of the banked DRAM and may cause failure of the banked DRAM. For example, each DRAM bank may require a particular power application, such as 1.5 V to operate properly. Each DRAM bank may continue to operate properly if xc2x110% of 1.5 V is applied, however for voltage deviations greater than 10% the performance of the bank degrades as the bank is not provided sufficient power. The controller preferably controls the maximum number of banks that are accessible during a single cycle such that power rail collapse does not occur.
According to one known method for controlling access to banks, a worst case analysis is calculated for a designed banked DRAM cache prior to manufacturing the banked DRAM cache, to determine the maximum number of banks which can be accessed during a single cycle. The worst case maximum is then fixed within the banked DRAM cache as the maximum number of accessible banks for each cycle. Performing worst case analysis adds to the design time of a banked DRAM cache before manufacture. In addition, the actual worst case maximum may increase or decrease in the manufactured product.
In view of the foregoing, it is therefore an object of the present invention to provide an improved method and system for power management within a data processing system.
It is another object of the present invention to provide an improved method and system for dynamic power management of a banked cache memory within a data processing system.
It is yet another object of the present invention to provide an improved method and system for dynamically selecting a maximum number of accessible banks of memory per cycle within a banked cache memory such that the number of bank accesses per cycle are maximized while maintaining an acceptable power application to each of the banks of memory of the banked cache memory.
In accordance with the method and system of the present invention, the application of power to each bank of memory of a banked cache memory is monitored in order to determine a maximum number of selectable bank accesses per cycle such that power application to each of the banks of memory is not degraded. No more than the maximum number of selectable bank accesses per cycle are permitted for subsequent cycles from among the banks of memory, such that the number of accessible banks of memory of a banked cache memory is dynamically selectable to maximize bank accesses per cycle while maintaining an acceptable power application to each of the banks of memory.
All objects, features and advantages of the present invention will become apparent in the following detailed written description.